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July 2000 PRELIMINARY
ML4832* Electronic Dimming Ballast Controller
GENERAL DESCRIPTION
The ML4832 is a complete solution for a dimmable/nondimmable, high power factor, high efficiency electronic ballast. The BiCMOS ML4832 contains controllers for "boost" type power factor correction as well as for a dimming ballast. The power factor circuit uses the average current sensing method with a gain modulator and overvoltage protection. This system produces a power factor of better than 0.99 with low input current THD at > 95% efficiency. Special care has been taken in the design of the ML4832 to increase system noise immunity by using a high amplitude oscillator, and a current-fed multiplier. An overvoltage protection comparator inhibits the PFC section in the event of a lamp out or lamp failure condition. The ballast section provides for programmable starting scenarios with programmable preheat and lamp out-ofsocket interrupt times. The IC controls lamp output through frequency modulation using lamp current feedback.
FEATURES
s s s s s s s s s s
Complete power factor correction and dimming ballast control in one IC Low distortion, high efficiency continuous boost, average current sensing PFC section Programmable start scenario for rapid or instant start lamps Lamp current feedback for dimming control Variable frequency dimming and starting Programmable restart for lamp out condition to reduce ballast heating Over-temperature shutdown replaces external heat sensor for safety PFC overvoltage comparator eliminates output "runaway" due to load removal Large oscillator amplitude and gain modulator improves noise immunity Low start-up current <0.5mA
(* Indicates part is End Of Life as of July 1, 2000)
BLOCK DIAGRAM
INTERRUPT 7 8 RSET RT/CT VARIABLE FREQUENCY OSCILLATOR OUTPUT DRIVERS RX/CX PRE-HEAT AND INTERRUPT TIMERS OUT A CONTROL & GATING LOGIC OUT B 14 LAMP FB LFB OUT 9 5 6
10
13
PFC OUT 2 4 3 1 18 IA OUT IA+ ISINE EA OUT EA-/OVP POWER FACTOR CONTROLLER UNDER-VOLTAGE AND THERMAL SHUTDOWN PGND VCC VREF GND
15
12 16 17 11
1
ML4832
PIN CONFIGURATION
ML4832 18-Pin DIP (P18)
EA OUT IA OUT ISINE IA+ LAMP FB LFB OUT RSET RT/CT INTERRUPT
1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10
ML4832 18-Pin SOIC (S18)
EA OUT IA OUT ISINE IA+ LAMP FB LFB OUT RSET RT/CT INTERRUPT 1 2 3 4 5 6 7 8 9 TOP VIEW 18 17 16 15 14 13 12 11 10
EA-/OVP VREF VCC PFC OUT OUT A OUT B P GND GND RX/CX
EA-/OVP VREF VCC PFC OUT OUT A OUT B P GND GND RX/CX
TOP VIEW
PIN DESCRIPTION
PIN# NAME FUNCTION PIN# NAME FUNCTION
1 2
EA OUT IA OUT
PFC error amplifier output and compensation node Output and compensation node of the PFC average current transconductance amplifier
9
INTERRUPT
Input used for lamp-out detection and restart. A voltage greater than 7.5 volts resets the chip and causes a restart after a programmable interval. Sets the timing for the preheat, dimming lockout, and interrupt Ground Power ground for the IC Ballast MOSFET drive output Ballast MOSFET drive output Power Factor MOSFET drive output Positive supply for the IC Buffered output for the 7.5V voltage reference Inverting input to PFC error amplifier and OVP comparator input
10 3 4 ISINE IA+ PFC gain modulator input Non-inverting input of the PFC average current transconductance amplifier and peak current sense point of the PFC cycle by cycle current limit comparator Inverting input of an error amplifier used to sense (and regulate) lamp arc current. Also the input node for dimming control. Output from the lamp current error transconductance amplifier used for lamp current loop compensation External resistor which sets oscillator FMAX, and RX/CX charging current Oscillator timing components 11 12 13 14 15 16 17 18
RX/CX GND P GND OUT B OUT A PFC OUT VCC VREF EA-/OVP
5
LAMP FB
6
LFB OUT
7 8
RSET RT/CT
2
ML4832
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Supply Current (ICC) ............................................... 60mA Output Current, Source or Sink (OUT A, OUT B, PFC OUT) DC ................................................................... 250mA Output Energy (capacitive load per cycle) ............... 1.5mJ Gain Modulator ISINE Input ..................................... 10mA Analog Inputs ....................................... -0.3V to VCC -2V IA+ Input Voltage .............................................. -3V to 2V Maximum Forced Voltage (EA OUT, LFB OUT) ................................ -0.3V to 7.7V Maximum Forced Current (EA OUT, IA OUT, LFB OUT) ............................ 20mA Maximum Forced Voltage (IA OUT) ................................................. -0.3V to 7.5V Junction Temperature ............................................. 150C Storage Temperature Range...................... -65C to 150C Lead Temperature (Soldering 10 sec.) ..................... 260C Thermal Resistance (qJA) Plastic PDIP ..................................................... 70C/W Plastic SOIC ................................................... 100C/W
OPERATING CONDITIONS
Temperature Range ML4832C .................................................. 0C to 85C
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, RSET = 22.1kW, RT = 15.8kW, CT = 1.5nF, C(VCC) = 1F, ISINE = 200A, VCC = 12.5V, TA = Operating Temperature Range (Note 1)
PARAMETER PFC CURRENT SENSE AMPLIFIER Small Signal Transconductance Output Low Output High Source Current ISINE = 0mA, VEA OUT = 0V, VIA+ = -0.3V, RL = ISINE = 1.5mA, VEA-/OVP = VIA+ = 0V, RL = ISINE = 1.5mA, VEA-/OVP = VIA+ = 0V, VIA OUT = 6V, TJ = 25C ISINE = 0mA, VIA OUT = 0.3V, VIA+ = -0.6V VEA OUT = 0V, VEA-/OVP = 5V, TJ = 25C 6.3 -0.05 40 90 0.2 6.8 -0.15 -0.25 120 0.4 CONDITIONS MIN TYP MAX UNITS
V V mA
Sink Current
0.03
0.07
0.16
mA
PFC VOLTAGE FEEDBACK AMPLIFIER/LAMP CURRENT AMPLIFIER Input Bias Current Small Signal Transconductance Input Voltage Range Output Low Output High Source Current VLAMP FB = VEA-/OVP = 3V, RL = VLAMP FB = VEA-/OVP = 2V, RL = VLAMP FB = VEA-/OVP = 0V, VEA OUT = VLFB OUT = 7V, TJ = 25C VLAMP FB = VEA-/OVP = 5V, VEA OUT = VLFB OUT = 0.3V, TJ = 25C 7.1 -0.06 30 -0.3 0.2 7.5 -0.15 -0.3 55 -1.0 90 5.0 0.4 7.8 -0.30 A
V V V mA
Sink Current
0.06
0.12
0.28
mA
W W
3
ML4832
ELECTRICAL CHARACTERISTICS
PARAMETER GAIN MODULATOR Output Voltage (VMUL) ISINE = 100A, VEA OUT = 3V ISINE = 300A, VEA OUT = 3V ISINE =100A, VEA OUT = 6V ISINE = 300A, VEA OUT = 6V Output Voltage Limit Offset Voltage ISINE = 1.5mA, VEA-/OVP = 0V ISINE = 0A, VEA-/OVP = 0V ISINE = 150A, VEA-/OVP = 3V ISINE Input Voltage PFC CURRENT -- LIMIT COMPARATOR Current-Limit Threshold Propagation Delay OSCILLATOR Initial Accuracy Voltage Stability Temperature Stability Total Variation Ramp Valley to Peak CT Charging Current VLAMP FB = 3V, VRT/CT = 2.5V, VRX/CX = 0.9V (Preheat) VLAMP FB = 3V, VRT/CT = 2.5V, RX/CX = Open CT Discharge Current Output Drive Deadtime REFERENCE SECTION Output Voltage Line regulation Load regulation Temperature stability Total Variation Output Noise Voltage Long Term Stability Line, load, temp 10Hz to 10kHz TJ = 125C, 1000 hrs 7.35 50 5 TA = 25C, IO = 1mA VCCZ - 4.0V < VCC < VCCZ - 0.5V 1mA < IO < 5mA 7.4 7.5 8 2 0.4 7.65 7.6 25 15 V mV mV % V V mV VRT/CT = 2.5V -90 -180 4.0 0.64 Line, temperature 69 2.5 -113 -230 5.5 0.91 -130 -260 7.0 1.30 TA = 25C VCCZ - 4.0V < VCC < VCCZ - 0.5V 72 76 1 2 83 80 kHz % % kHz V A A mA s 100mV step and 100mV overdrive -0.85 -1.0 100 -1.15 V ns ISINE = 200A 0.8 1.4 0.9 85 260 200 600 1 1.1 15 15 1.8 mV mV mV mV V mV mV V
(Continued)
CONDITIONS MIN TYP MAX UNITS
PREHEAT AND INTERRUPT TIMER (RX = 680KW, CX = 4.7F) Initial Preheat Period Subsequent Preheat Period Start Period Interrupt Period Pin 10 Charging Current -24 0.8 0.7 1.2 5.7 -28 -33 s s s s A
4
ML4832
ELECTRICAL CHARACTERISTICS (Continued)
PARAMETER CONDITIONS MIN TYP MAX UNITS PREHEAT AND INTERRUPT TIMER (RX = 680KW, CX = 4.7F) CONTINUIED Pin 10 Open Circuit Voltage Pin 10 Maximum Voltage Input Bias Current Preheat Lower Threshold Preheat Upper Threshold Interrupt Recovery Threshold Start Period End Threshold INTERRUPT INPUT Interrupt Threshold Input Bias Current RSET Voltage OVP COMPARATOR OVP Threshold Hysteresis Propagation Delay OUTPUTS Output Voltage Low IOUT = 20mA IOUT = 200mA Output Voltage High IOUT = -20mA IOUT = -200mA Output Voltage Low in UVLO Output Rise/Fall Time UNDER-VOLTAGE LOCKOUT AND BIAS CIRCUITS IC Shunt Voltage (VCCZ) Start-up Current Operating Current ICC = 15mA VCC = Start-up threshold -0.2V VCC = 12.5V, VIA+ = 0V, VEA-/OVP = VLAMP FB = 2.3V, IA OUT = open RT = 16.2kW, RSET = 22.1kW VCC = 12.5V, CL = 0 14.2 15.0 0.34 5.5 15.8 0.48 8.0 V mA mA IOUT = 10mA, VCC 8V CL = 1000pF 20
VCC - 0.2 VCC - 2.0
VCC < Start-up threshold
0.4 7.0
0.7 7.3
1.0 7.7 0.1
V V A V V V V
VRX/CX = 1.2V 1.05 4.4 1.05 6.05 1.22 4.77 1.22 6.6
1.36 5.15 1.36 7.35
7.15
7.4
7.65 0.1
V A V
2.4
2.5
2.6
2.65 0.20
2.75 0.25 1.4
2.85 0.27
V V s
0.1 1.0
VCC - 0.1 VCC - 1.0
0.2 2.0
V V V V
0.2
V ns
Start-up Threshold Shutdown Threshold Shutdown Temperature (TJ) Hysteresis (TJ)
Note 1: Limits are guaranteed by 100% testing, sampling or correlation with worst case test conditions.
VCC - 1.2 VCCZ - 1.0 VCC - 0.8 VCC - 5.5 VCCZ - 5.0 VCC - 4.5
V V C C
120 30
5
ML4832
FUNCTIONAL DESCRIPTION
OVERVIEW The ML4832 consists of an average current controlled continuous boost power factor front end section with a flexible ballast control section. Start-up and lamp-out retry timing are controlled by the selection of external timing components, allowing for control of a wide variety of different lamp types. The ballast section controls the lamp power using frequency modulation (FM) with additional programmability provided to adjust the VCO frequency range. This allows for the IC to be used with a variety of different output networks. POWER FACTOR SECTION The ML4832 power factor section is an average current sensing boost mode PFC control circuit which is architecturally similar to that found in the ML4821. For detailed information on this control architecture, please refer to Application Note 16 and the ML4821 data sheet. GAIN MODULATOR The ML4832 gain modulator provides high immunity to the disturbances caused by high power switching. The rectified line input sine wave is converted to a current via a series resistor. In this way, small amounts of ground noise produce an insignificant effect on the reference to the PWM comparator. The output of the gain modulator appears on the positive terminal of the IA amplifier to form the reference for the current error amplifier. Please refer to Figure 1.
VMUL =
ISINE x 1VEA-0.7V6 34mA .
(1)
where: ISINE is the current in the dropping resistor, VEA is the output of the error amplifier (Pin 1). The output of the gain modulator is limited to 1.0V.
7
RSET VARIABLE FREQUENCY OSC + - + UNDER-VOLTAGE AND THERMAL SHUTDOWN - VREF 2.5V
LFB OUT
6
10
RX/CX
PREHEAT TIMER
LAMP FB INTERRUPT
5 9
16 17 11
VCC VREF GND
2
IA OUT
RT/CT
8
7k - 4 IA + -VMUL+ + 7k - -1V ISINE EA OUT +
+ - PWM (PFC) S
R PFC OUT Q 15
OUT A Q
14
T 3 1 18 GAIN MODULATORS Q
OUT B
13
- EA -/OVP 2.5V - + 2.75V + OVP
P GND
12
Figure 1. ML4832 Block Diagram
6
ML4832
FUNCTIONAL DESCRIPTION (Continued)
AVERAGE CURRENT AND OUTPUT VOLTAGE REGULATION The PWM regulator in the PFC control section will act to offset the positive voltage caused by the multiplier output by producing an offsetting negative voltage on the current sense resistor at IA+. A cycle-by-cycle current limit is included to protect the MOSFET from high speed current transients. When the voltage at IA+ goes negative by more than 1V, the PWM cycle is terminated. For more information on compensating the average current and boost voltage error amplifier loops, see ML4821 data sheet. OVERVOLTAGE PROTECTION AND INHIBIT The OVP pin serves to protect the power circuit from being subjected to excessive voltages if the load should change suddenly (lamp removal). A divider from the high voltage DC bus sets the OVP trip level. When the voltage on EA-/OVP exceeds 2.75V, the PFC transistors are inhibited. The ballast section will continue to operate. TRANSCONDUCTANCE AMPLIFIERS The PFC voltage feedback, PFC current sense, and the loop current amplifiers are all implemented as operational transconductance amplifiers. They are designed to have low small signal forward transconductance such that a large value of load resistor (R1) and a low value ceramic capacitor (<1F) can be used for AC coupling (C1) in the frequency compensation network. The compensation network shown in Figure 2 will introduce a zero and a pole at:
fZ =
1 2 R1C1
fP =
1 2 R1C 2
(2)
Figure 3 shows the output configuration for the operational transconductance amplifiers. A DC path to ground or VCC at the output of the transconductance amplifiers will introduce an offset error.
18 2.5V
- + R1 C2
C1
Figure 2. Compensation Network
CURRENT MIRROR IN OUT gmVIN 2 io = gmVIN
iO
IQ + IQ - gmVIN 2
0 Linear Slope Region
VIN Differential
IN
OUT CURRENT MIRROR
Figure 3. Output Configuration
Figure 4. Transconductance Amplifier Characteristics
7
ML4832
FUNCTIONAL DESCRIPTION (Continued)
The magnitude of the offset voltage that will appear at the input is given by VOS = io/gm. For an io of 1mA and a gm of 0.05 mhos the input referred offset will be 20mV. Capacitor C1 as shown in Figure 2 is used to block the DC current to minimize the adverse effect of offsets. Slew rate enhancement is incorporated into all of the operational transconductance amplifiers in the ML4832. This improves the recovery of the circuit in response to power up and transient conditions. The response to large signals will be somewhat non-linear as the transconductance amplifiers change from their low to high transconductance mode. This is illustrated in Figure 4. BALLAST OUTPUT SECTION The IC controls output power to the lamps via frequency modulation with non-overlapping conduction. This means that both ballast output drivers will be low during the discharging time tDIS of the oscillator capacitor CT. OSCILLATOR The VCO frequency ranges are controlled by the output of the LFB amplifier. As lamp current decreases, LFB OUT rises in voltage, causing the CT charging current to decrease, thereby causing the oscillator frequency to decrease. Since the ballast output network attenuates high frequencies, the power to the lamp will be increased. The oscillator frequency is determined by the following equations:
FOSC =
and
1 t CHG + tDIS
(3)
t CHG = RT C T In
V V
REF
REF
+ ICH R T - VTL + ICH RT - VTH

(4)
The oscillator's minimum frequency is set when ICH = 0 where:
FOSC
1 0.51x RT C T
(5)
This assumes that tCHG >> tDIS. When LFB OUT is high, ICH = 0 and the minimum frequency occurs. The charging current varies according to two control inputs to the oscillator: 1. The output of the preheat timer 2. The voltage at LFB OUT In preheat condition, charging current is fixed at
ICHG (PREHEAT) =
25 . RSET
(6)
17
VREF
VREF
RT
ICHG
CONTROL
CLOCK
RT/CT 8 1.25/3.75 CT 5.5mA + -
tDIS VTH = 3.75V
tCHG
CT VTL = 1.25V
Figure 5. Oscillator Block Diagram and Timing
8
ML4832
FUNCTIONAL DESCRIPTION (Continued)
In running mode, charging current decreases as the VPIN6 rises from 0V to VOH of the LAMP FB amplifier. The highest frequency will be attained when ICHG is highest, which is attained when LFB OUT is at 0V: To help reduce ballast cost, the ML4832 includes a temperature sensor which will inhibit ballast operation if the IC's junction temperature exceeds 120C. In order to use this sensor in lieu of an external sensor, care should be taken when placing the IC to ensure that it is sensing temperature at the physically appropriate point in the ballast. The ML4832's die temperature can be estimated with the following equation:
ICHG(0) =
5 R SET
(7)
Highest lamp power, and lowest output frequency are attained when LFB OUT is at its maximum output voltage (VOH). In this condition, the minimum operating frequency of the ballast is set per (5) above. For the IC to be used effectively in dimming ballasts with higher Q output networks a larger CT value and lower RT value can be used, to yield a smaller frequency excursion over the control range (VLFB OUT). The discharge current is set to 5.5mA. Assuming that IDIS >> IRT:
T J TA x PD x 65 C / W
STARTING, RE-START, PREHEAT AND INTERRUPT
(9)
The lamp starting scenario implemented in the ML4832 is designed to maximize lamp life and minimize ballast heating during lamp out conditions. The circuit in Figure 7 controls the lamp starting scenarios: Filament preheat and lamp out interrupt. CX is charged with a current of IRSET/4 and discharged through RX. The voltage at CX is initialized to 0.7V (VBE) at power up. The time for CX to rise to 4.8V is the filament preheat time. During that time, the oscillator charging current (ICHG) is 2.5/RSET. This will produce a high frequency for filament preheat, but will not produce sufficient voltage to ignite the lamp. After cathode heating, the inverter frequency drops to FMIN causing a high voltage to appear to ignite the lamp. If the voltage does not drop when the lamp is supposed to have ignited, the lamp voltage feedback coming into pin 9 rises to above VREF, the CX charging current is shut off and the inverter is inhibited until CX is discharged by RX to the 1.2V threshold. Shutting off the inverter in this manner prevents the inverter from generating excessive heat when
t DIS(VCO) 600 x CT
(8)
IC BIAS, UNDER-VOLTAGE LOCKOUT AND THERMAL SHUTDOWN The IC includes a shunt regulator which will limit the voltage at VCC to 15V (VCCZ). The IC should be fed with a current limited source, typically derived from the ballast transformer auxiliary winding. When VCC is below VCCZ - 1.1V, the IC draws less than 0.48mA of quiescent current and the outputs are off. This allows the IC to start using a "bleed resistor" from the rectified AC line.
VCC VCCZ VON VOFF
10 CX 1.2/4.8 6.8 + 1.2/6.8 - R DIMMING LOCKOUT INHIBIT Q S RX/CX + HEAT - 0.625 RSET
ICC 5.5mA
t
RX
0.34mA t
9
INT VREF
- +
Figure 6. Typical VCC and ICC Waveforms when the ML4832 is Started with a Bleed Resistor from the Rectified AC Line and Bootstrapped from an Auxiliary Winding.
Figure 7. Lamp Preheat and Interrupt Timers
9
ML4832
FUNCTIONAL DESCRIPTION (Continued)
the lamp fails to strike or is out of socket. Typically this time is set to be fairly long by choosing a large value of RX. LFB OUT is ignored by the oscillator until CX reaches 6.8V threshold. The lamps are therefore driven to full power and then dimmed. The CX pin is clamped to about 7.5V. A summary of the operating frequencies in the various operating modes is shown below. OPERATING MODE Preheat Dimming Lock-out DIMMING CONTROL OPERATING FREQUENCY [F(MAX) to F(MIN)] 2 F(MIN) F(MIN) TO F(MAX)
6.8 4.8 RX/CX 1.2 .65 0 HEAT
DIMMING LOCKOUT
7.5 INT
INHIBIT
Figure 8. Lamp Starting and Restart Timing
10
ML4832
TYPICAL APPLICATIONS
Figures 9 and 10 show ballast schematics, both nondimming and dimming. These are power-factor corrected 60W ballasts designed to operate two series connected F32T8 fluorescent lamps. Both Schematics, Figures 9 and 10, are of previously published ML4831 circuits that have been modified for ML4832 compatibility. The value changes and component additions made for ML4832 compatibility were for different amplifier compensation, bootstrap/bias and protection and do not effect the validity of the circuit description, operational information or equations.
TO CONVERT FROM AN EXISTING NON-DIMMING ML4831 TO THE ML4832: Resistors Change: R4 R7 R18 R13 R14 Add: R24 R22 R23 Delete: Capacitors Change: C5 C7 C11 C12 C18 C20 Add: Magnetics Change: T1 to TSD-882 C23 to to to to to to 10nF, 63V, 10% ceramic 180pF, 100V, 5% ceramic 1nF, 100V, 10% ceramic 100nF, 100V, 10% ceramic 100F, 16V, 20% electrolytic 100F, 25V, 20% electrolytic 33nF, 50V, 20% ceramic R9 to to to to to 51kW, 1/4 W, 5% carbon film 866kW, 1/4 W, 1%, metal film 75kW, 1/4 W, 5%, carbon film 470W, 1/4 W, 5%, carbon film 5.76kW, 1/4 W, 1%, metal film 499kW, 1/4 W, 5%, carbon film 75kW, 1/4 W, 5%, carbon film 51W, 1/4 W, 5%, carbon film 100W, 1/4 W, 5%, carbon film R6, R7 to
TO CONVERT FROM AN EXISTING DIMMING ML4831 TO THE ML4832: Resistors Change: R4 R7 R18 R13 R14 R26 Add: R32 R30 R31 Delete: Capacitors Change: C5 C7 C25 C12 C24 C20 Add: Diodes Delete: Magnetics Change: T1 to TSD-882 D10, D13 C27 C26 to to to to to to 10nF, 63V, 10% ceramic 180pF, 100V, 5% ceramic 1nF, 100V, 10% ceramic 100nF, 100V, 10% ceramic 100F, 16V, 20% electrolytic 100F, 25V, 20% electrolytic 33nF, 50V, 20% ceramic 100nF, 100V, 10% ceramic R9 to to to to to to 51kW, 1/4 W, 5% carbon film 866kW, 1/4 W, 1%, metal film 75kW, 1/4 W, 5%, carbon film 470W, 1/4 W, 5%, carbon film 5.76kW, 1/4 W, 1%, metal film 499kW, 1/4 W, 5%, carbon film 200kW, 1/4 W, 5%, carbon film 75kW, 1/4 W, 5%, carbon film 51W, 1/4 W, 5%, carbon film 100W, 1/4 W, 5%, carbon film R6, R11 to
11
C23 33nF 6 13 12 11 10 7 8 9 C6 2.2nF R5 15.4k C4 R15 0.1F 324k
ML4832
12
TP4 D1 1A 7 T1 8 D2 1A D9 1A 7 Q3 IRF820 T3 R24 75k 1 8 TP1 C22 33nF C17 1F R22 51 TP2 R6 866k C18 100F R18 470 R23 100 D13 0.1A R19 51 6 7 4 3 2 1 9 8 C9 33nF C8 4700pF B B R R Y Y 2 C10 47F R13 5.76k D7 1A Q1 2.5A R12 442k R7 75k 6 3 R17 51 9 T2 Q2 IRF820 10 D12 1A R20 442k D4 1A D5 1A R1 1.0 D6 1A R8 22 C20 R11 100F 866k TP5 R10 11.5k 1 18 17 16 15 14 D11 IN4148 TP3 R2 1k R16 1k D8 IN4148 C19 C13 10F C14 C15 C16 0.22F 0.22F 100pF R3 9.1k C21 0.001F 2 3 4 R14 499k 5 R21 5k R4 51k
ML4832
HOT
F1
L1
220 VAC
D3 C1* C3 1A 2.2nF 0.15F
C2 2.2nF
NEUTRAL
*Note: Only One Chassis Ground
Figure 9. 220V Non-Dimming Ballast
C7 C5 C12 C11 10nF 100nF 1nF 180pF
TP4 D15 1A D3 1A 7 T1 8 D4 1A D2 1A D9 1A Q1 2.5A Q3 2.5A R32 75k R19 51 1 8 TP1 C22 0.33F R6 866k C17 1F R31 100 R18 470 R30 51 C24 100F C27 33nF R16 10k R10 11.5k 1 18 17 16 15 14 13 12 11 10 D16 5.1V R29 1.3k D11 0.1A R26 200k R20 10k 9 5 C21 1F TP3 R15 324k C13 10F C14 0.22F C15 0.22F C16 100pF R22 11k 6 C6 2.2nF R5 15.4k C26 100nF R24 64.9k 3 2 + - IC1 + - 4 7 8 1 R28 20k 2 3 4 5 6 7 R2 4.3k R3 220k 8 R25 5k 6 7 T4 7 2 R12 442k R7 75k 6 3 9 D7 1A Q2 2.5A T2 R23 442k 10 R17 51 D1 1A
HOT
F1
L1
220 VAC
C1* 2.2nF
C3 0.15nF C2 2.2nF
NEUTRAL D5 1A R11 866k R8 22 R1 1.0 D6 1A C20 100F C10 47F R13 5.76k
L2
2 1 4 3 9 8 C9 15nF C8 4700pF T5 TP5 5 1 6 10
R R Y Y B B
*Note: Only One Chassis Ground
ML4832
Figure 10. 220V Dimming Ballast
TP2
R27 200k
R4 R14 499k 51k
D8 0.1A
C4 C12 C25 C7 C5 10nF 100nF 1nF 180pF 3.3F
ML4832
13
ML4832
PHYSICAL DIMENSIONS inches (millimeters)
Package: P18 18-Pin PDIP
0.890 - 0.910 (22.60 - 23.12) 18
PIN 1 ID
0.240 - 0.260 0.295 - 0.325 (6.09 - 6.61) (7.49 - 8.26)
0.045 MIN (1.14 MIN) (4 PLACES)
1 0.050 - 0.065 (1.27 - 1.65) 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN)
0.170 MAX (4.32 MAX)
0.125 MIN (3.18 MIN)
0.016 - 0.022 (0.40 - 0.56)
SEATING PLANE
0 - 15
0.008 - 0.012 (0.20 - 0.31)
Package: S18 18-Pin SOIC
0.449 - 0.463 (11.40 - 11.76) 18
0.291 - 0.301 0.398 - 0.412 (7.39 - 7.65) (10.11 - 10.47) PIN 1 ID
1 0.024 - 0.034 (0.61 - 0.86) (4 PLACES) 0.050 BSC (1.27 BSC) 0.095 - 0.107 (2.41 - 2.72) 0 - 8
0.090 - 0.094 (2.28 - 2.39)
0.012 - 0.020 (0.30 - 0.51)
SEATING PLANE
0.005 - 0.013 (0.13 - 0.33)
0.022 - 0.042 (0.56 - 1.07)
0.009 - 0.013 (0.22 - 0.33)
14
ML4832
ORDERING INFORMATION
PART NUMBER ML4832CP (End of Life) ML4832CS (Obsolete) TEMPERATURE RANGE 0C to 85C 0C to 85C PACKAGE Molded PDIP (P18) SOIC (S18)
(c) Micro Linear 1999.
is a registered trademark of Micro Linear Corporation. All other trademarks are the property of their respective owners.
DS4832-01
2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295
Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174; 5,767,653; 5,777,514; 5,793,168; 5,798,635; 5,804,950; 5,808,455; 5,811,999; 5,818,207; 5,818,669; 5,825,165; 5,825,223; 5,838,723; 5.844,378; 5,844,941. Japan: 2,598,946; 2,619,299; 2,704,176; 2,821,714. Other patents are pending. Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application.
02/19/99 Printed in U.S.A.
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